Modeling and design of a low-power injection-locked frequency divider in 90nm CMOS for 60GHz applications

@article{Katz2011ModelingAD,
  title={Modeling and design of a low-power injection-locked frequency divider in 90nm CMOS for 60GHz applications},
  author={Alex Katz and Ofir Degani and Eran Socher},
  journal={2011 IEEE 11th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems},
  year={2011},
  pages={61-64}
}
This paper describes the modeling and design considerations of a low-power divide-by-two injection-locked frequency divider (ILFD) for 60GHz frequency synthesizer applications implemented in 90nm CMOS process. The paper proposes a divider's locking range model based on mixing analysis. The design uses a capacitor bank for the divider band selection and tail current injection. Measured results of the designed divider show minimum power consumption of 1.32mW and locking range 2.5GHz at an input… CONTINUE READING

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