Modeling and characterization of the system-level Power Delivery Network for a dual-core ARM Cortex-A57 cluster in 28nm CMOS

@article{Das2015ModelingAC,
  title={Modeling and characterization of the system-level Power Delivery Network for a dual-core ARM Cortex-A57 cluster in 28nm CMOS},
  author={Shidhartha Das and Paul N. Whatmough and David M. Bull},
  journal={2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)},
  year={2015},
  pages={146-151}
}
Power delivery is a well-known challenge for high-end microprocessor systems. Comparatively, mobile computing platforms typically consume order-of-magnitude lower currents, but economic and volume constraints limit the quality of the Power Delivery Network. In addition, the trend towards GHz+ operating frequencies and the ubiquity of low-power techniques such as clock-gating and power-gating, make these systems susceptible to pathological AC transients. Consequently, mobile computing systems… CONTINUE READING
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