Modeling and analysis of III–V logic FETs for devices and circuits: Sub-22nm technology III–V SRAM cell design


A compact model of III–V HFETs is developed for digital logic circuit applications such as a 6T-SRAM cell. We study sub-22nm technology III–V SRAM circuit design via III–V MOSFETs with thin high-k dielectric for low gate tunneling current, and optimized extrinsic structure for minimum parasitic capacitance. We investigate the drawbacks… (More)
DOI: 10.1109/ISQED.2010.5450553


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