Modeling and Separate Extraction Technique for Gate Bias-Dependent Parasitic Resistances and Overlap Length in MOSFETs

@article{Lee2015ModelingAS,
  title={Modeling and Separate Extraction Technique for Gate Bias-Dependent Parasitic Resistances and Overlap Length in MOSFETs},
  author={Jungmin Lee and Hagyoul Bae and Jun Seok Hwang and Jaeyeop Ahn and Jun Tae Jang and Jinsoo Yoon and Sung-Jin Choi and Dong Myong Kim},
  journal={IEEE Transactions on Electron Devices},
  year={2015},
  volume={62},
  pages={1063-1067}
}
We report a technique for separate extraction of extrinsic source/drain (S/D) resistances (R<sub>Se</sub>/R<sub>De</sub>) and gate bias (V<sub>GS</sub>)-dependent but channel length (L)-independent intrinsic source/drain (R<sub>Si</sub>/R<sub>Di</sub>) resistances for the overlap region in MOSFETs. For extraction of the overlap length (L<sub>ov</sub>) in the heavily doped S/D regions, an analytical capacitance model for the depletion region is employed with the gate-to-source and gate-to-drain… CONTINUE READING