Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation


We present an efficient technique for finding the mean and variance of the full-chip leakage of a candidate design, while considering logic-structures and both die-to-die and within-die process variations, and taking into account the spatial correlation due to within-die variations. Our model uses a "random gate" concept to capture high-level characteristics of a candidate chip design, which are sufficient to determine its leakage. We show empirically that, for large gate count, the set of all chip designs that share the same high level characteristics have approximately the same leakage, with very small error. Therefore, our model can be used as either an <i>early</i> or a <i>late</i> estimator of leakage, with high accuracy. In its simplest form, we show that full-chip leakage estimation reduces to finding the area under a scaled version of the within-die channel length auto-correlation function, which can be done in constant time.

DOI: 10.1145/1278480.1278504

Extracted Key Phrases

6 Figures and Tables

Cite this paper

@article{Heloue2007ModelingAE, title={Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation}, author={Khaled R. Heloue and Navid Azizi and Farid N. Najm}, journal={2007 44th ACM/IEEE Design Automation Conference}, year={2007}, pages={93-98} }