Modeling and Design of a CMOS Low Drop-out (LDO) Voltage Regulator

Abstract

The proposed CMOS Low Dropout (LDO) regulator has been designed and simulated using ON semiconductor’s 0.5μ CMOS process. This paper illustrates the design criteria and corresponding analysis relevant to LDO. The experimental result shows that, it regulates an output voltage at 3.3V from a 3.5V supply, with a minimum dropout voltage of 200mV at a maximum… (More)

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