Ubolli “On the Generation of Large Passive Macro models for Complex Interconnect Structures
- Stefano. G.T, Andrea
- In Proceedings of IEEE Trans. On Adv.Packaging,
A high speed RLCG circuit interconnects has become faultless and has suited essential to address signal integrity. For faultless representation a full wave exploration is required. Typically circuit simulation of RLC interconnect CPU is lavish. This paper discusses RLCG full wave exploration using frequency shift techniques. The results shown are efficient. It can also be done by Fourier series analysis. A logical interconnects representation is introduce based on Fourier series exploration satisfactory for periodic signal such as clock signal. In this representation, the far end time domain zone waveform is estimates by the super-impose of various sinusoids. The fifth and the higher harmonics are ignored when closed form response of the 50% lag. The representation is applied to the various allocated coupled interconnect and interconnected trees. Good exactness is detecting intermediately within the SPICE and model simulation. The computation complication of the representation is linear with the number of harmonics.