Modeling Spin Coating Over Topography and Uniformity Improvements Through Fill Patterns for Advanced Packaging Technologies

@article{Lang2019ModelingSC,
  title={Modeling Spin Coating Over Topography and Uniformity Improvements Through Fill Patterns for Advanced Packaging Technologies},
  author={Christopher I. Lang and Duane S. Boning},
  journal={IEEE Transactions on Semiconductor Manufacturing},
  year={2019},
  volume={32},
  pages={62-69}
}
  • C. Lang, D. Boning
  • Published 2019
  • Materials Science
  • IEEE Transactions on Semiconductor Manufacturing
An empirical model is proposed for predicting surface variations following dielectric spin coating as applied to existing underlying topography in redistribution layer fabrication. Test structures that represent a wide range of underlying feature widths, spacings, and heights are designed and fabricated. These are coated with multiple thicknesses of polyimide, and their surfaces are profiled and analyzed. An empirical model based on spatial filtering over underlying features is developed, with… Expand
Modeling and Controlling Layout Dependent Variations in Semi-Additive Copper Electrochemical Plating
  • C. Lang, D. Boning
  • Materials Science
  • IEEE Transactions on Semiconductor Manufacturing
  • 2019
An empirical model is proposed for predicting layout dependent thickness variations in the semi-additive copper electrochemical plating (ECP) process. These variations are believed to be caused byExpand

References

SHOWING 1-10 OF 11 REFERENCES
Spin coating modeling and planarization using fill patterns for advanced packaging technologies
An empirical model is proposed for the dielectric spin coating (DSC) and curing process applied to existing underlying topographies in redistribution layers (RDLs). Test structures that represent aExpand
Modelling pattern dependent variations in semi-additive copper electrochemical plating: AP/DFM: Advanced patterning / design for manufacturability
  • C. Lang, D. Boning
  • Materials Science
  • 2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)
  • 2018
An empirical model is proposed for predicting layout-dependent thickness variations in the semi-additive copper electrochemical plating (ECP) process. These variations are believed to be caused byExpand
Leveling of thin films over uneven substrates during spin coating
The planarization, that is leveling, of 1–4 μm thick liquid epoxy films over 25–200 μm wide isolated trenches on a silicon substrate during spin coating is determined by photochemically hardening theExpand
Pattern dependent modeling of electroplated copper profiles
  • T. Park, T. Tugbawa, D. Boning
  • Materials Science
  • Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461)
  • 2001
Copper electroplated profiles exhibit pattern dependent topography. We propose a methodology for the characterization and modeling of feature scale copper step heights and the height of copper arrayExpand
SPATIAL VARIATION IN SEMICONDUCTOR PROCESSES: MODELING FOR CONTROL
TLDR
In several semiconductor processes, models of both wafer-level and die-level spatial dependencies will become increasingly important for effective multi-objective process control that encompasses uniformity, throughput, and environmental goals. Expand
Pattern Based Prediction for Plasma Etch
Plasma etching is a key process for pattern formation in integrated circuit (IC) manufacturing. Unfortunately, pattern-dependent nonuniformities arise in plasma etching processes due to localizedExpand
Design, Modeling, Fabrication and Characterization of 2–5- $\mu \text{m}$ Redistribution Layer Traces by Advanced Semiadditive Processes on Low-Cost Panel-Based Glass Interposers
  • Hao Lu, R. Furuya, +4 authors R. Tummala
  • Materials Science
  • IEEE Transactions on Components, Packaging and Manufacturing Technology
  • 2016
This paper presents the latest advances in extending semiadditive process (SAP) methods to 2-5 μm lines and spaces, achieved using dry film photoresists on thin glass substrates, toward meeting theExpand
Polymer-based fine pitch Cu RDL to enable cost-effective re-routing for 2.5D interposer and 3D-IC
In this paper, 2 metal layers, very fine pitch Cu RDL process using spin-on photo-pattern-able polymer based material was demonstrated, with Cu wiring of a minimum of 2-μm/2-μm line/space (L/S) andExpand
Fabrication and Assembly of Cu-RDL-Based 2.5-D Low-Cost Through Silicon Interposer (LC–TSI)
TLDR
A through silicon interposer (TSI) fabrication process and detailed characterization and measurement results of redistribution layers and through silicon vias for low-cost 2.5-D integration enables high-density interdie connections with low cost. Expand
High-performance integrated fan-out wafer level packaging (InFO-WLP): Technology and system integration
Integrated fan-out wafer-level packaging (InFO-WLP) technology with state-of-the-art inductors (quality factor of 42 and self-resonance frequency of 16 GHz) has been demonstrated for heterogeneousExpand
...
1
2
...