# Modeling Algorithms in SystemC and ACL2

@inproceedings{OLeary2014ModelingAI, title={Modeling Algorithms in SystemC and ACL2}, author={John W. O'Leary and David M. Russinoff}, booktitle={International Workshop on the ACL2 Theorem Prover and Its Applications}, year={2014} }

We describe the formal language MASC, based on a subset of SystemC and intended for modeling algorithms to be implemented in hardware. By means of a special-purpose parser, an algorithm coded in SystemC is converted to a MASC model for the purpose of documentation, which in turn is translated to ACL2 for formal verification. The parser also generates a SystemC variant that is suitable as input to a high-level synthesis tool. As an illustration of this methodology, we describe a proof of…

## 5 Citations

### Formal Verification of Arithmetic RTL: Translating Verilog to C++ to ACL2

- Computer ScienceACL2
- 2020

This paper describes the RAC language, the translation process, and some techniques that facilitate formal analysis of the resulting ACL2 code, enabling a mechanically checked proof of correctness with respect to a formal architectural specification.

### Engineering a Formal, Executable x86 ISA Simulator for Software Verification

- Computer ScienceProvably Correct Systems
- 2017

This work describes a formal, executable model of the x86 instruction-set architecture and presents design decisions made during model development to optimize both validation and verification, i.e., efficiency of both simulation and reasoning.

### Using ACL2 in the Design of Efficient, Verifiable Data Structures for High-Assurance Systems

- Computer ScienceACL2
- 2018

The Intermediate Verification Language for the toolchain features code generation to mainstream programming languages, as well as GPU-based and hardware-based realizations, and ACL2 is used to develop the efficient yet verifiable data structure design.

### Python facilitates the rapid prototyping and hw/sw verification of processor centric SoCs for FPGAs

- Computer Science2016 IEEE International Symposium on Circuits and Systems (ISCAS)
- 2016

This paper shows how SysPy can also facilitate high-level functional verification of a SoC when used as an Architectural Description Language (ADL), helping a designer make decisions about key architectural features early in the design phase.

### Verified Hardware/Software Co-Assurance: Enhancing Safety and Security for Critical Systems

- Computer Science2020 IEEE International Systems Conference (SysCon)
- 2020

This work describes how the Russinoff-O’Leary Restricted Algorithmic C (RAC) toolchain is used to translate the authors' JSON filter to ACL2, present proofs of correctness for its associated data types, and describe validation and performance results obtained through the use of concrete test vectors.

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