Model Checking for a First-Order Temporal Logic Using Multiway Decision Graphs (MDGs)

@article{Xu2004ModelCF,
  title={Model Checking for a First-Order Temporal Logic Using Multiway Decision Graphs (MDGs)},
  author={Ying Xu and Xiaoyu Song and Eduard Cerny and Otmane A{\"i}t Mohamed},
  journal={Comput. J.},
  year={2004},
  volume={47},
  pages={71-84}
}
description of state machine is a model used for describing hardware designs at the RTL. Using ASMs, a data value can be represented by a single variable of abstract type, rather than by a vector of Boolean variables, and a data operation is represented by an uninterpreted function symbol. The model checking method based on a first-order linear-time temporal logic as developed in this paper allows to verify properties on designs represented by ASMs. Thus, it is necessary to review first the… CONTINUE READING

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