Model Checking VHDL with CV

@inproceedings{Dharbe1998ModelCV,
  title={Model Checking VHDL with CV},
  author={David D{\'e}harbe and Subash Shankar and Edmund M. Clarke},
  booktitle={FMCAD},
  year={1998}
}
This article describes a prototype implementation of a symbolic model checker for a subset of VHDL. The model checker applies a number of techniques to reduce the search space, thus allowing for efficient verification of real circuits. We have completed an initial release of the VHDL model checker and have used it to verify complex circuits, including the control logic of a commercial RISC microprocessor. 

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Graph-Based Algorithms for Boolean Function Manipulation

IEEE Transactions on Computers • 1986
View 4 Excerpts
Highly Influenced

Formal Methods in System Design, volume

R. K. Brayton, E. M. Clarke, P. A. Subrahmanyam, editors
1995
View 1 Excerpt

Formal Semantics for VHDL, volume 307 of Series in Engineering and Computer Science

C. Delgado Kloos, P. Breuer, editors
1995
View 1 Excerpt

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