Mixed-precision in-memory computing

@article{LeGallo2017MixedprecisionIC,
  title={Mixed-precision in-memory computing},
  author={Manuel Le Gallo and Abu Sebastian and Roland Mathis and Matteo Manica and Heiner Giefers and Tomas Tuma and Costas Bekas and Alessandro Curioni and Evangelos Eleftheriou},
  journal={Nature Electronics},
  year={2017},
  volume={1},
  pages={246-253}
}
As complementary metal–oxide–semiconductor (CMOS) scaling reaches its technological limits, a radical departure from traditional von Neumann systems, which involve separate processing and memory units, is needed in order to extend the performance of today’s computers substantially. [] Key Method In this hybrid system, the computational memory unit performs the bulk of a computational task, while the von Neumann machine implements a backward method to iteratively improve the accuracy of the solution. The…
Memory devices and applications for in-memory computing
TLDR
This Review provides an overview of memory devices and the key computational primitives enabled by these memory devices as well as their applications spanning scientific computing, signal processing, optimization, machine learning, deep learning and stochastic computing.
Hybrid Analog-Digital In-Memory Computing
TLDR
A new paradigm called hybrid analog-digital in-memory computing is proposed, capable of performing matrix-vector multiplication with both high energy-efficiency and precision and evaluated using applications from the domains of structural engineering, mathematics, and statistics.
Device and Circuit Architectures for In‐Memory Computing
TLDR
An overview of IMC in terms of memory devices and circuit architectures is provided, including typical architectures for neural network accelerators, content addressable memory (CAM), and novel circuit topologies for general‐purpose computing with low complexity.
Temperature Compensation Schemes for In-Memory Computing using Phase-Change Memory
TLDR
This work describes a temperature compensation method that applies to resistive crossbar arrays and its realization as a peripheral circuit and derives array-level temperature compensation functions that are remarkably effective for projected phase-change memory devices.
Perspectives on Emerging Computation-in-Memory Paradigms
TLDR
This work introduces ReRAMs in terms of their novel computing paradigms and present ReRAM-specific design flows and addresses the various circuit opportunities and challenges related to reliability and fault tolerance associated with them.
In-Memory Computing with Resistive Memory Circuits: Status and Outlook
TLDR
This work presents the status and outlook on the RRAM for analog computing, where the precision of the encoded coefficients, such as the synaptic weights of a neural network, is one of the key requirements.
Computational phase-change memory: beyond von Neumann computing
TLDR
This article presents a comprehensive review of in-memory computing using phase-change memory (PCM) devices and suggests that emerging post-CMOS, non-volatile memory devices based on resistance-based information storage are particularly well suited.
In‐Memory Vector‐Matrix Multiplication in Monolithic Complementary Metal–Oxide–Semiconductor‐Memristor Integrated Circuits: Design Choices, Challenges, and Perspectives
TLDR
A qualitative and quantitative analysis of several key existing challenges in implementing high‐capacity, high‐volume RS memories for accelerating the most computationally demanding computation in machine learning (ML) inference, that of vector‐matrix multiplication (VMM), is presented.
Logic-in-Memory Based on an Atomically Thin Semiconductor
TLDR
This work explores large-area grown MoS2 as an active channel material for developing logic-in-memory devices and circuits based on floating-gate field-effect transistors (FGFET) and highlights the potential of atomically thin semiconductors for the development of next-generation low-power electronics.
CIM-SIM: Computation In Memory SIMuIator
TLDR
The CIM-SIM is introduced, an open source simulator written in SystemC, which is capable of simulating the functional behaviour of non-volatile memory architectures and includes the definition of a set of technology-agnostic nano-instructions.
...
1
2
3
4
5
...

References

SHOWING 1-10 OF 61 REFERENCES
Temporal correlation detection using computational phase-change memory
TLDR
The results of using a large-scale demonstration of computational phase change memory by performing high-level computational primitives using one million PCM devices show that this co-existence of computation and storage at the nanometer scale could enable ultra-dense, low-power, and massively-parallel computing systems.
Projected phase-change memory devices
TLDR
This work designed and fabricated projected memory devices based on the phase-change storage mechanism and convincingly demonstrate the concept through detailed experimentation, supported by extensive modelling and finite-element simulations.
Arithmetic and Biologically-Inspired Computing Using Phase-Change Materials
TLDR
This work provides, for the first time, an experimental proof-of-principle of such a phase-change material-based “processor” that demonstrates reliable experimental execution of the four basic arithmetic processes of addition, multiplication, division and subtraction, with simultaneous storage of the result.
Mixed-precision training of deep neural networks using computational memory
TLDR
This work proposes a mixed-precision architecture that combines a computational memory unit storing the synaptic weights with a digital processing unit and an additional memory unit accumulating weight updates in high precision that delivers classification accuracies comparable to those of floating-point implementations without being constrained by challenges associated with the non-ideal weight update characteristics of emerging resistive memories.
Accumulation-Based Computing Using Phase-Change Memories With FET Access Devices
TLDR
This letter presents non-von Neumann arithmetic processing that exploits the accumulative property of phase-change memory (PCM) cells and demonstrates efficient factorization using PCM cells, a technique that could pave the way for massively parallelized computations.
Stochastic Memristive Devices for Computing and Neuromorphic Applications
TLDR
This work demonstrates memristor-based stochastic bitstreams in both time and space domains, and shows that an array of binary memristors can act as a multi-level "analog" device for neuromorphic applications.
Programming algorithms for multilevel phase-change memory
TLDR
The proposed schemes are based on iterative write-and-verify algorithms that exploit the unique programming characteristics of PCM in order to achieve significant improvements in resistance-level packing density, robustness to cell variability, programming latency, energy-per-bit and cell storage capacity.
Memristive Boltzmann machine: A hardware accelerator for combinatorial optimization and deep learning
  • M. N. Bojnordi, Engin Ipek
  • Computer Science
    2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)
  • 2016
TLDR
A new class of hardware accelerators for large-scale combinatorial optimization and deep learning based on memristive Boltzmann machines is examined based on recently developed resistive RAM (RRAM) technology, achieving 57x higher performance and 25x lower energy with virtually no loss in the quality of the solution to the optimization problems.
‘Memristive’ switches enable ‘stateful’ logic operations via material implication
TLDR
Bipolar voltage-actuated switches, a family of nonlinear dynamical memory devices, can execute material implication (IMP), which is a fundamental Boolean logic operation on two variables p and q such that pIMPq is equivalent to (NOTp)ORq.
Dot-product engine for neuromorphic computing: Programming 1T1M crossbar to accelerate matrix-vector multiplication
TLDR
The Dot-Product Engine (DPE) is developed as a high density, high power efficiency accelerator for approximate matrix-vector multiplication, invented a conversion algorithm to map arbitrary matrix values appropriately to memristor conductances in a realistic crossbar array.
...
1
2
3
4
5
...