Mitigating Multi-Bit-Upset With Well-Slits in 28 nm Multi-Bit-Latch


This paper proposes a technique that mitigates multi-bit-upset (MBU) in multi-bit-latch (MBL) without performance degradation by applying well-slits. The area overhead in an MBL macro for processor design, which includes a clock buffer and a checker, is only 5.4% in a 28 nm technology. Sixty-hour accelerated neutron irradiation test observed no MBUs in the… (More)


13 Figures and Tables

Cite this paper

@article{Uemura2013MitigatingMW, title={Mitigating Multi-Bit-Upset With Well-Slits in 28 nm Multi-Bit-Latch}, author={Taiki Uemura and Takashi Kato and Hideya Matsuyama and Masanori Hashimoto}, journal={IEEE Transactions on Nuclear Science}, year={2013}, volume={60}, pages={4362-4367} }