Minimizing peak power consumption during scan testing: test pattern modification with X filling heuristics

@article{Badereddine2006MinimizingPP,
  title={Minimizing peak power consumption during scan testing: test pattern modification with X filling heuristics},
  author={Nabil Badereddine and Patrick Girard and Serge Pravossoudovitch and Christian Landrault and Arnaud Virazel and H.-J. Wundcrlich},
  journal={International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.},
  year={2006},
  pages={359-364}
}
Scan architectures, though widely used in modern designs, are expensive in power consumption. In this paper, we discuss the issues of excessive peak power consumption during scan testing. We show that taking care of high current levels during the test cycle (i.e. between launch and capture) is highly relevant to avoid noise phenomena such as IR-drop or ground bounce. We propose a solution based on power-aware assignment of don't care bits in deterministic test patterns. For ISCAS'89 and ITC'99… CONTINUE READING
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