Minimizing Power Consumption in CMOS

@inproceedings{Narwariya2018MinimizingPC,
  title={Minimizing Power Consumption in CMOS},
  author={Anand Singh Narwariya and Shyam Akashe and Dimitri A. Antoniadis and Ingvar Aberg and C. N. Chleirigh and Osama M. Nayfeh and Alireza Khakifirooz and Pranshu Sharma and Anjali Sharma and R K Raman Singh and Tanvi Sood and Rajesh Mehra},
  year={2018}
}
Full Subtractor using Self Controllable Voltage Level (SVL) Technique is designed in this paper. The circuit can supply an increased dc voltage to an active-load circuit required or can decrease the dc voltage supplied to a load circuit under standby mode is developed. Full Subtractor is a consumed low power and low Leakage as compare to conventional design… CONTINUE READING