Minimization of chip size and power consumption of high-speed VLSI buffers

@inproceedings{Zhou1997MinimizationOC,
  title={Minimization of chip size and power consumption of high-speed VLSI buffers},
  author={Dengji Zhou and X. Y. Liu},
  booktitle={ISPD},
  year={1997}
}
In this paper, we study optimal bu er design in high-performance VLSI systems. Speci cally, we design a bu er for a given load such that chip area and power dissipation are minimal while circuit delay is no greater than a given upper bound. The explored direction, i.e., to minimize chip area and power consumption with circuit speed as a constraint, is a more realistic setting in practical VLSI design than conventional design objectives, where minimal circuit delay is usually sought. In fact, an… CONTINUE READING