Microarchitecture soft error vulnerability characterization and mitigation under 3D integration technology

@article{Zhang2008MicroarchitectureSE,
  title={Microarchitecture soft error vulnerability characterization and mitigation under 3D integration technology},
  author={Wangyuan Zhang and Tao Li},
  journal={2008 41st IEEE/ACM International Symposium on Microarchitecture},
  year={2008},
  pages={435-446}
}
As semiconductor processing techniques continue to scale down, transient faults, also known as soft errors, are increasingly becoming a reliability threat to high-performance microprocessors fabricated using state-of-the-art CMOS technologies. Emerging 3D chip integration techniques leverage vertically stacked structures to reduce on-chip wire delay and have shown the capability of overcoming interconnect bottlenecks as well as reducing power consumption. While the benefits of 3D die stacking… CONTINUE READING