Microarchitecture optimizations for exploiting memory-level parallelism

  title={Microarchitecture optimizations for exploiting memory-level parallelism},
  author={Yuan Chou and Brian Fahs and Santosh G. Abraham},
  journal={Proceedings. 31st Annual International Symposium on Computer Architecture, 2004.},
The performance of memory-bound commercial applicationssuch as databases is limited by increasing memory latencies. Inthis paper, we show that exploiting memory-level parallelism(MLP) is an effective approach for improving the performance ofthese applications and that microarchitecture has a profound impacton achievable MLP. Using the epoch model of MLP, we reasonhow traditional microarchitecture features such as out-of-orderissue and state-of-the-art microarchitecture techniques suchas… CONTINUE READING
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