Microarchitecture of the Godson-2 Processor

@article{Hu2005MicroarchitectureOT,
  title={Microarchitecture of the Godson-2 Processor},
  author={W. Hu and Fuxing Zhang and Zusong Li},
  journal={Journal of Computer Science and Technology},
  year={2005},
  volume={20},
  pages={243-249}
}
The Godson project is the first attempt to design high performance general-purpose microprocessors in China. This paper introduces the microarchitecture of the Godson-2 processor which is a 64-bit, 4-issue, out-of-order execution RISC processor that implements the 64-bit MIPS-like instruction set. The adoption of the aggressive out-of-order execution techniques (such as register mapping, branch prediction, and dynamic scheduling) and cache techniques (such as non-blocking cache, load… Expand
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References

SHOWING 1-7 OF 7 REFERENCES
The HP PA-8000 RISC CPU
TLDR
The PA-8000 RISC CPU is the first of a new generation of Hewlett-Packard microprocessors designed for high-end systems, and features an aggressive, four-way, superscalar implementation, combining speculative execution with on-the-fly instruction reordering. Expand
The Mips R10000 superscalar microprocessor
The Mips R10000 is a dynamic, superscalar microprocessor that implements the 64-bit Mips 4 instruction set architecture. It fetches and decodes four instructions per cycle and dynamically issues themExpand
Introducing the IA-64 Architecture
TLDR
The motivation, operation, and benefits of the major features of IA-64 are examined and it is found that instruction-level parallelism (ILP) can be exploited for further performance increases. Expand
The Alpha 21264 microprocessor
TLDR
A unique combination of high clock speeds and advanced microarchitectural techniques, including many forms of out-of-order and speculative execution, provide exceptional core computational performance in the 21264. Expand
UltraSPARC-III: designing third-generation 64-bit performance
TLDR
The UltraSPARC-III is the third generation of Sun Microsystems' most powerful microprocessors, which are at the heart of Sun's computer systems and ensures compatibility with all existing SPARC applications and the Solaris operating system. Expand
POWER4 system microarchitecture
TLDR
The processor microarchitecture as well as the interconnection architecture employed to form systems up to a 32-way symmetric multiprocessor are described. Expand
Computer Architecture: A Quantitative Approach
This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most importantExpand