This paper presents a novel methodology for design of operational computational devices, realizing a diversity of condition-controlled loop algorithmic structures. The synthesis of such a structure takes in count just the necessary for the computation signal changes, which makes the synthesis of controlling finite state machine unnecessary. Thus the resulting controlling circuit is tightly coupled with the logic one. In this sense the structure can be defined as self-controlling and can be part of micro-pipeline structure with certain delay. The methodology can be applied when designing either synchronous or asynchronous structures. The structures in either case are as fast as possible because they can be organized in pipeline fashion.
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