Methodologies for Layout Decomposition and Mask Optimization: A Systematic Review

Abstract

As the transistor feature size keeps shrinking, manufacturability has become an urgent issue in semiconductor industry. In order to improve the manufacturability, various resolution enhancement techniques have been proposed, among which layout decomposition and mask optimization have been considered as the most powerful solutions in advanced technology nodes. Different from many previous survey papers that categorize literatures by type of manufacturing process, we argue that different manufacturing scenarios can share similar mathematical models. This paper carefully summarizes a series of methodologies that have been successfully applied to VLSI layout decomposition and mask optimization problems.

9 Figures and Tables

Cite this paper

@inproceedings{Ma2017MethodologiesFL, title={Methodologies for Layout Decomposition and Mask Optimization: A Systematic Review}, author={Yuzhe Ma and Xuan Zeng and Bei Yu and Hong Kong}, year={2017} }