Mesh-of-Trees and Alternative Interconnection Networks for Single-Chip Parallelism

@article{Balkan2009MeshofTreesAA,
  title={Mesh-of-Trees and Alternative Interconnection Networks for Single-Chip Parallelism},
  author={Aydin O. Balkan and Gang Qu and Uzi Vishkin},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  year={2009},
  volume={17},
  pages={1419-1432}
}
In single-chip parallel processors, it is crucial to implement a high-throughput low-latency interconnection network to connect the on-chip components, especially the processing units and the memory units. In this paper, we propose a new mesh of trees (MoT) implementation of the interconnection network and evaluate it relative to metrics such as wire complexity, total register count, single switch delay, maximum throughput, tradeoffs between throughput and latency, and post-layout performance… CONTINUE READING
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