A new multilevel hierarchical MFPGA and its suitable configuration tools
In this paper we present a new clustered mesh FPGA architecture where each cluster local interconnect is implemented as an MFPGA tree network . Unlike previous clustered mesh architectures, the mesh of tree allows us to consider large clusters sizes (thanks to MFPGA depopu-lated local interconnect). Experimentation shows that we obtain a reduction of 14% in switches number and 2 times in the placement and routing run time. Furthermore, compared to MFPGA, the mesh of tree achieves full routability of all MCNC benchmarks since we can easily control both clusters LUTs occupation and mesh channel width.