Mesa - Sidewall Gate Leakage in InAlAs / InGaAs Heterostructure Field - Effect Transistors

Abstract

InAIAslInGaAs HFET’s fabricated by conventional mesa isolation have a potential parasitic gate-leakage path where the gate metallization overlaps the exposed channel edge at the mesa sidewall. We have unmistakably proven the existence of this path by fabricating special heterojunction diodes with different mesa-sidewall gate-metal overlap lengths. We find that sidewall leakage is a function of the crystallographic orientation of the sidewall, and increases with channel thickness, sidewall overlap area, and InAs mole fraction in the channel. In HFET’s fabricated alongside the diodes, sidewall leakage increased the subthreshold and forward gate leakage currents, and reduced the breakdown voltage. ETEROSTRUCTURE Field-Effect Transistors H (HFET’s) from the InAlAs /InGaAs /InP material systems are of great interest for long-wavelength optical and ultra-high-frequency microwave telecommunication applications. Both Modulation-Doped FET’s (MODFET’s) and Metal-Insulator Doped-channel FET’s (MIDFET’s) have shown excellent high-frequency performance [ l ] , [2]. MIDFET’s have, in addition, shown excellent high-voltage potential [3]. Enriching the InAs mole fraction in the InGaAs channel of these HFET’s has resulted in substantial device improvement [2J, [4]. This is due to the enhanced electron transport properties of InAs-enriched InGaAs [5]. Fabrication of these HFET’s by conventional mesa isolation, however, results in sidewalls where the InGaAs channel is exposed and comes in contact with the gate metallization running up the mesa (Fig. 1). Even though the sidewall contact area can easily be several orders of magnitude smaller than the gate area, the low Schottkybarrier height of metals with Ino,5,Gao,47As (0.2 eV) [6] potentially results in a significant leakage path from the gate to the channel. In AlGaAs/GaAs HFET’s, mesasidewall gate leakage, or sidewall leakage for short, Manuscript received November 26, 1991; revised April 17, 1992. This work was funded by the Joint Services Electronics Program through the Research Laboratory of Electronics under Contract DAAAL-03-89-C-000 I and the C. S . Draper Laboratory under Contract DL-H-404180. The review of this paper was arranged by Associate Editor M. Shur. S . R. Bahl and J . A. del Alamo are with the Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA 02139. M. H . Leary was with the Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA 02139. He is now with Comell University, Ithaca, NY 14853. IEEE Log Number 9201832. f GATE Fig. 1. Perspective of HFET, showing the sidewall-leakage path at the gate-metallmesa-sidewall overlap. should be insignificant due to the higher Schottky-barrier height of GaAs with metals ( 0.75 eV) [7]. For typical InAlAs /InGaAs HFET’s, however, researchers have acknowledged that sidewall leakage causes excessive gateleakage current [4], [8]-[ 101 and severely degraded breakdown voltage [4], [9]. To study the effect of sidewall leakage in our MIDFET’s, we have fabricated, alongside them, specially designed test structures with varying lengths L, of mesasidewall/gate-metal overlap or sidewall overlap. Since the heavy doping in the channel of these test structures enhances tunneling through the barrier, they make good tools to study sidewall leakage. Here, we present what we believe is the first comprehensive study of mesa-sidewall gate leakage in InAlAs /InGaAs HFET’s fabricated using conventional mesa isolation. We provide unequivocal evidence of sidewall leakage and show its impact on device characteristics.

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Cite this paper

@inproceedings{Leary2004MesaS, title={Mesa - Sidewall Gate Leakage in InAlAs / InGaAs Heterostructure Field - Effect Transistors}, author={Michael H. Leary}, year={2004} }