Memristor modelling

@article{Muthuswamy2014MemristorM,
  title={Memristor modelling},
  author={B. Muthuswamy and J. Jevtic and H. Iu and C. K. Subramaniam and K. Ganesan and V. Sankaranarayanan and K. Sethupathi and Hyongsuk Kim and M. Sah and L. Chua},
  journal={2014 IEEE International Symposium on Circuits and Systems (ISCAS)},
  year={2014},
  pages={490-493}
}
In this paper, we show a simple circuit setup for experimentally plotting the v - i non-transversal pinched-hysteresis Lissajous fingerprint of a physical memristor - the common fluorescent gas discharge tube. The setup helped us investigate the effects of physical parasitics (inductors and capacitors) on the memristor v - i. 
A Generic Model of Memristors With Parasitic Components
TLDR
A generic model of memristive systems, which can emulate the behavior of real Memristive devices is proposed, by adding four parasitic circuit elements, namely, asmall capacitance, a small inductance, aSmall DC current source, and a small DC voltage source, to the memristIVE device. Expand
Analysis and generation of chaos using compositely connected coupled memristors.
TLDR
A new way through which memristor-based circuit dynamics can be influenced by tuning the coupling strength between memristors without changing other circuit parameters is provided. Expand
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TLDR
A five-component autonomous chaotic oscillator of jerky type, hitherto the simplest of its kind, using only one operational amplifier, is reported, emulating a Colpitts-like chaotic circuit. Expand
Spike neural network architecture with memristive synapses using predictive Cmos model
TLDR
Two types of Integrate and Fire Neuron (if) (IF) are presented using 32nm CMOS technology simulated in LTspice with BSIM4v4 model designed by Berkley University and applying predictive parameters provided by Predictive Technology Model (PTM). Expand

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