Memristor MOS Content Addressable Memory (MCAM): Hybrid Architecture for Future High Performance Search Engines

@article{Eshraghian2011MemristorMC,
  title={Memristor MOS Content Addressable Memory (MCAM): Hybrid Architecture for Future High Performance Search Engines},
  author={K. Eshraghian and Kyoung-Rok Cho and O. Kavehei and Soon-Ku Kang and D. Abbott and S. Kang},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  year={2011},
  volume={19},
  pages={1407-1417}
}
Large-capacity content addressable memory (CAM) is a key element in a wide variety of applications. The inevitable complexities of scaling MOS transistors introduce a major challenge in the realization of such systems. Convergence of disparate technologies, which are compatible with CMOS processing, may allow extension of Moore's Law for a few more years. This paper provides a new approach towards the design and modeling of Memory resistor (Memristor)-based CAM (MCAM) using a combination of… Expand
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References

SHOWING 1-10 OF 37 REFERENCES
Writing to and reading from a nano-scale crossbar memory based on memristors.
TLDR
A design study for a nano-scale crossbar memory system that uses memristors with symmetrical but highly nonlinear current-voltage characteristics as memory elements and simulation results show the feasibility of these writing and reading procedures. Expand
Architectural evaluation of 3D stacked RRAM caches
  • D. L. Lewis, H. Lee
  • Engineering, Computer Science
  • 2009 IEEE International Conference on 3D System Integration
  • 2009
TLDR
This paper presents a point-by-point comparison between DRAM and this new RRAM, based on both existent and expected near-term memristor devices, and considers the case of a die-stacked 3D memory that is integrated onto a logic die and evaluates which memory is best suited for the job. Expand
Low-Leakage Storage Cells for Ternary Content Addressable Memories
  • N. Mohan, M. Sachdev
  • Engineering, Computer Science
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • 2009
TLDR
Two novel ternary storage cells are presented that exploit the unique properties of TCAMs for reducing the cell leakage and can perform read and write operations in less than 3.6 ns. Expand
The fourth element: Insights into the memristor
New developments in nanoelectronics are promising a new generation of computing, which has greater focus on device capabilities. Further to many applications of memristors in artificial intelligenceExpand
A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy
TLDR
A high density SRAM in 65 nm CMOS that uses an 8T bit-cell to achieve a minimum operating voltage of 350 mV, and the plaguing area-offset tradeoff in modern sense-amplifiers is alleviated using redundancy. Expand
Fault tolerance techniques for high capacity RAM
TLDR
New types of redundancy based on divided bit-line (DBL), and divided word- line (DWL) techniques are proposed in this work and can improve the memory fabrication yield significantly. Expand
Four-dimensional address topology for circuits with stacked multilayer crossbar arrays
We present a topological framework that provides a simple yet powerful electronic circuit architecture for constructing and using multilayer crossbar arrays, allowing a significantly increasedExpand
Content-addressable memory (CAM) circuits and architectures: a tutorial and survey
TLDR
This paper surveys recent developments in the design of large-capacity content-addressable memory (CAM) and reviews CAM-design techniques at the circuit level and at the architectural level. Expand
Match Sensing Using Match-Line Stability in Content-Addressable Memories (CAM)
This paper presents a match-line (ML) sensing scheme that distinguishes a match from a miss by first shunting every ML with a fixed negative resistance, then exciting the MLs with an initial charge,Expand
The missing memristor found
TLDR
It is shown, using a simple analytical example, that memristance arises naturally in nanoscale systems in which solid-state electronic and ionic transport are coupled under an external bias voltage. Expand
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