Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures

  title={Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures},
  author={Rajeev Balasubramonian and David H. Albonesi and Alper Buyuktosunoglu and Sandhya Dwarkadas},
Conventional microarchitectures choose a single memory hierarchy design point targeted at the average application. In this paper, we propose a cache and TLB layout and design that leverages repeater insertion to provide dynamic low-cost configurability trading off size and speed on a per application phase basis. A novel configuration management algorithm dynamically detects phase changes and reacts to an application’s hit and miss intolerance in order to improve memory hierarchy performance… CONTINUE READING
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Technology Scaling and Its Impact on Cache Delay

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