Memory access pattern-aware DRAM performance model for multi-core systems

@article{Choi2011MemoryAP,
  title={Memory access pattern-aware DRAM performance model for multi-core systems},
  author={Hyojin Choi and Jongbok Lee and Wonyong Sung},
  journal={(IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE},
  year={2011},
  pages={66-75}
}
The DRAM latency modeling is complex because most chips contain row-buffers and multiple banks to exploit patterns of DRAM accesses. As a result, the latency of DRAM access not only depends on the circuit timing parameters but also memory access patterns. This study derives an analytical model that predicts the DRAM access performance using DRAM timing and memory access pattern parameters. As a performance metric, the bank busy time of DRAM is used. The pattern parameters employed represent… CONTINUE READING
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