Memory Modeling in ESL-RTL Equivalence Checking

@article{Klbl2007MemoryMI,
  title={Memory Modeling in ESL-RTL Equivalence Checking},
  author={Alfred K{\"o}lbl and Jerry R. Burch and Carl Pixley},
  journal={2007 44th ACM/IEEE Design Automation Conference},
  year={2007},
  pages={205-209}
}
When designers create RTL models from a system-level specification, arrays in the system-level model are often implemented as memories in the RTL. Knowing the correspondence between ESL arrays and RTL memories can significantly reduce the complexity of a formal equivalence check between the ESL model and the RTL. In practice, however, handling memory mappings in ESL-RTL equivalence checking is non-trivial for the following reasons: First, because of a lack of bit-accurate data-types in the… CONTINUE READING
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