Memory-Efficient Hardware Architecture of 2-D Dual-Mode Lifting-Based Discrete Wavelet Transform

@article{Hsia2013MemoryEfficientHA,
  title={Memory-Efficient Hardware Architecture of 2-D Dual-Mode Lifting-Based Discrete Wavelet Transform},
  author={Chih-Hsien Hsia and Jen-Shiun Chiang and Jing-Ming Guo},
  journal={IEEE Transactions on Circuits and Systems for Video Technology},
  year={2013},
  volume={23},
  pages={671-683}
}
Memory requirements (for storing intermediate signals) and critical path are essential issues for 2-D (or multidimensional) transforms. This paper presents new algorithms and hardware architectures to address the above issues in 2-D dual-mode (supporting 5/3 lossless and 9/7 lossy coding) lifting-based discrete wavelet transform (LDWT). The proposed 2-D dual-mode LDWT architecture has the merits of low transpose memory (TM), low latency, and regular signal flow, making it suitable for very… CONTINUE READING
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