Memory-Efficient Hardware Architecture of 2-D Dual-Mode Lifting-Based Discrete Wavelet Transform

  title={Memory-Efficient Hardware Architecture of 2-D Dual-Mode Lifting-Based Discrete Wavelet Transform},
  author={Chih-Hsien Hsia and Jen-Shiun Chiang and Jing-Ming Guo},
  journal={IEEE Transactions on Circuits and Systems for Video Technology},
Memory requirements (for storing intermediate signals) and critical path are essential issues for 2-D (or multidimensional) transforms. This paper presents new algorithms and hardware architectures to address the above issues in 2-D dual-mode (supporting 5/3 lossless and 9/7 lossy coding) lifting-based discrete wavelet transform (LDWT). The proposed 2-D dual-mode LDWT architecture has the merits of low transpose memory (TM), low latency, and regular signal flow, making it suitable for very… CONTINUE READING
Highly Cited
This paper has 40 citations. REVIEW CITATIONS


Publications citing this paper.
Showing 1-10 of 27 extracted citations


Publications referenced by this paper.
Showing 1-10 of 30 references

An efficient VLSI architecture for 2-D DWT using lifting scheme

  • J.-S. Chiang, C.-H. Hsia
  • Proc. IEEE Int. Conf. Syst. Signals, Apr. 2005…
  • 2005
Highly Influential
7 Excerpts

Energy efficient novel architectures for the lifting-based discrete wavelet transform

  • H. Varshney, M. Hasan, S. Jain
  • IET Image Process., vol. 1, no. 3, pp. 305–310…
  • 2007
Highly Influential
4 Excerpts

High-speed and memoryefficient VLSI design of 2-D DWT for JPEG2000 applications

  • K. Mei, N. Zheng, H. van de Wetering
  • IET Electron. Lett., vol. 42, no. 16, pp. 907–908…
  • 2006
Highly Influential
4 Excerpts

Similar Papers

Loading similar papers…