Memory Architecture of 3D Vertical Gate (3DVG) NAND Flash Using Plural Island-Gate SSL Decoding Method and Study of it's Program Inhibit Characteristics

@article{Chang2012MemoryAO,
  title={Memory Architecture of 3D Vertical Gate (3DVG) NAND Flash Using Plural Island-Gate SSL Decoding Method and Study of it's Program Inhibit Characteristics},
  author={Kuo-Pin Chang and Hang-Ting Lue and Chih-Ping Chen and Chieh-Fang Chen and Y. Y. Chen and Yi-Hsuan Hsiao and Chih-Chang Hsieh and Yen-Hao Shih and Tahone Yang and Kuang-Chao Chen and Chun-Hsiung Hung and Chih-Yuan Lu},
  journal={2012 4th IEEE International Memory Workshop},
  year={2012},
  pages={1-4}
}
The memory architecture of 3D vertical gate (3DVG) NAND Flash using plural island-gate SSL decoding method is discussed in detail. In order to provide a good array efficiency, 3DVG shares the wordlines (WL) in vertical direction, and BL's in lateral direction. In order to correctly decode the array, every channel BL has its own island-gate SSL device for the control. Meanwhile, many channel BL's are grouped together in one unit, and the staircase BL contacts are formed in order to decode… CONTINUE READING
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