Measurement and Analysis of Parasitic Capacitance in FinFETs with High-k Dielectrics and Metal-Gate Stack

Abstract

FinFET is one of the promising device architectures for sub-32nm CMOS technology nodes. These non-planar devices benefit from near bulk-Si processing and improved control of short channels due to quasi gate-all-around operation. Their device operation is well studied and optimized in last half decade by various research groups. In this paper, we help… (More)
DOI: 10.1109/VLSI.Design.2009.80

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