Maximizing throughput over parallel wire structures in the deep submicrometer regime

  title={Maximizing throughput over parallel wire structures in the deep submicrometer regime},
  author={Dinesh Pamunuwa and Lirong Zheng and Hannu Tenhunen},
  journal={IEEE Trans. VLSI Syst.},
In a parallel multiwire structure, the exact spacing and size of the wires determine both the resistance and the distribution of the capacitance between the ground plane and the adjacent signal carrying conductors, and have a direct effect on the delay. Using closed-form equations that map the geometry to the wire parasitics and empirical switch factor based delay models that show how repeaters can be optimized to compensate for dynamic effects, we devise a method of analysis for optimizing… CONTINUE READING
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Publications referenced by this paper.
Showing 1-10 of 53 references

On-Chip Inductance in High Speed Integrated Circuits

Y. I. Ismail, E. G. Friedman
Norwell, MA: Kluwer, • 2001
View 2 Excerpts

On-chip wiring design challenges for gigahertz operation

A. Deutsch, P. W. Coteus, +5 authors P. J. Restle
IEEE Special Issue on Interconnections, vol. 89, pp. 529–555, Apr. 2001. • 2001
View 1 Excerpt

The future of wires

R. Ho, K. W. Mai, M. A. Horowitz
IEEE Special Issue on Interconnections , vol. 89, pp. 490–504, Apr. 2001. • 2001
View 1 Excerpt

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