Magic's Incremental Design-Rule Checker

@article{Taylor1984MagicsID,
  title={Magic's Incremental Design-Rule Checker},
  author={George S. Taylor and John K. Ousterhout},
  journal={21st Design Automation Conference Proceedings},
  year={1984},
  pages={160-165}
}
The Magic VLSI layout editor contains an incremental design-rule checker. When the circuit is changed, only the modified areas are rechecked. The checker runs continuously in background to keep information about design-rule violations up-to-date. This paper describes the basic rule checker, which operates on edges in the layout, and the techniques used to perform incremental checking on hierarchical designs. 

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