Macro-models for high-level area and power estimation on FPGAs

@article{Jiang2006MacromodelsFH,
  title={Macro-models for high-level area and power estimation on FPGAs},
  author={Tianyi Jiang and Xiaoyong Tang and Prithviraj Banerjee},
  journal={IJSPM},
  year={2006},
  volume={2},
  pages={12-19}
}
As more and more complex applications are implemented on FPGAs, high-level design tools are needed to reduce the design time. A good high-level synthesis tool usually has an automated design space exploration pass to determine the effects of various compiler optimizations on the area and power of the synthesized hardware. Such a pass needs early estimation of area and power. Towards this end, we have developed high-level equation based area and power macro-models for various RTL level operators… CONTINUE READING

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