MU6-G. a new design to achieve mainframe performance from a mini-sized computer

  title={MU6-G. a new design to achieve mainframe performance from a mini-sized computer},
  author={DAVID B. G. Edwards and Alan E. Knowles and John V. Woods},
  booktitle={ISCA '80},
MU6-G is a high performance machine useful for general or scientific applications. Its order code and architecture are designed to be sympathetic to the needs of the operating system and to both the compilation and execution of programs written in high level languages and to support a word size suitable for high precision scientific computations. Advanced technology, coupled with simplicity of design, is used to achieve a high and more readily predictable performance. Innovative features… 

Figures from this paper

MU6V: a parallel vector processing system

A prototype model based on 68000 microprocessors, in which vector orders are emulated as "extracodes", has been constructed and an example algorithm is presented.

On the Design and Performance of Pipelined Architectures TR 87-022 August , 1987

An alternative theory of pipelining is introduced, which is called Context Flow, and it is shown how it can be used to construct efficient parallel systems.

On the design and performance of conventional pipelined architectures

The aim of this paper is to present a critical review of conventional pipelined architectures and put some well-known problems in sharp relief, and introduce an alternative theory of pipelining, which is called Context Flow.

An instruction fetch unit for a graph reduction machine

An instruction fetch unit is described for such an architecture that provides a high throughput of instructions, low latency and adequate elasticity in the instruction pipeline, achieved by a hybrid instruction set and a decoupled RISC architecture.

The design of protocols for high performance in a networked computing environment (mainframe configurations)

The principles of the protocols and the details of their implementation in an experimental system are described and the software tools developed to support the implementation are also described.

The University of Manchester MU5 Project

  • R. Ibbett
  • Computer Science
    IEEE Ann. Hist. Comput.
  • 1999
A history of the development of the MU5 hardware and the way in which the system was brought to life is presented, which explains some of the thinking that went into the design of MU5 and reflects on the success of the project.

Addressing Mechanisms for Large Virtual Memories

Hardware and software mechanisms to implement a paged virtual memory which can be efficiently accessed by large addresses and an implementation of these techniques for a capability-based computer, MONADS-PC, is described.

Design of a Hih-Speed Square Root Multiply and Divide Unit

Radix-4 algorithms for square root and division are developed and are shown to be suitable for implementing as a unified hardware unit which evaluates square root, division, and multiplication.

Architectural and Operating System Support for Orthogonal Persistence

This paper argues that conventional architectures provide an inappropriate base for persistent object systems and that the authors must look towards new architectures if they are to achieve ac- ceptable performance.



The MU5 instruction pipeline

A significant improvement in performance is obtained by this technique although detailed requirements of the order code deteriorate the performance in practice.

The development of the MU5 computer system

An overall view of the complete MU5 complex is presented together with a brief indication of its performance and the aims and ideas for MU5 are discussed.

A Synthetic Benchmark

Most scientific programming is performed in high level languages, so these measurements will be a better guide to the machine’s capabilities than measuremen ts based on use of low level languages.

One-Level Storage System

An automatic system which in principle can be applied to any combination of two storage systems so that the combination can be regarded by the machine user as a single level is described.

MUSS—a portable operating system

This paper describes a technique for producing a machine‐independent operating system with a high level of performance. The technique is based on the definition of a hypothetical ideal machine, which

The MU5 Computer System

By reading mu5 computer system, you can take more advantages with limited budget.


Assessing the Power of an Order Code