Efficient Totally-Ordered Subset Generation, with Application in Partial Reconfiguration
A decoder is a hardware module that expands an x-bit input into an n-bit output, where x ≪ n. It can be viewed as producing a set P of subsets of an n-element set Z<inf>n</inf>. If this set P can be altered by the user, the decoder is said to be configurable. In this paper we propose a class of configurable decoders (called “mapping-unit” based decoders or simply MU-decoders) that facilitate efficient selection of elements in an FPGA (in general, in any chip). Current solutions for this selection use either (a) a fixed (non-reconfigurable) decoder that lacks the flexibility to generate many subsets quickly, or (b) a large look-up table (LUT) which is flexible, but too expensive. The proposed class of MU-decoders offers a range of trade-offs between flexibility of subset generation and cost. Specifically, we show that for any fixed order of gate cost, the MU-decoder can produce any set of subsets that the LUT decoder can; in addition, the MU-decoder can exploit any available structure in the application at hand to produce many more subsets than the LUT decoder. We illustrate this ability in the context of totally ordered sets of subsets.