MRPB: Memory request prioritization for massively parallel processors

@article{Jia2014MRPBMR,
  title={MRPB: Memory request prioritization for massively parallel processors},
  author={Wenhao Jia and Kelly A. Shaw and Margaret Martonosi},
  journal={2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)},
  year={2014},
  pages={272-283}
}
Massively parallel, throughput-oriented systems such as graphics processing units (GPUs) offer high performance for a broad range of programs. They are, however, complex to program, especially because of their intricate memory hierarchies with multiple address spaces. In response, modern GPUs have widely adopted caches, hoping to providing smoother reductions in memory access traffic and latency. Unfortunately, GPU caches often have mixed or unpredictable performance impact due to cache… CONTINUE READING
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