MOS transistor characteristics and its dependence of plasma charging degradation on the test structure layout for a 0.13µm CMOS technology

@article{Martin2010MOSTC,
  title={MOS transistor characteristics and its dependence of plasma charging degradation on the test structure layout for a 0.13µm CMOS technology},
  author={Andreas Martin and Rolf-Peter Vollertsen and Hans Reisinger},
  journal={2010 IEEE International Integrated Reliability Workshop Final Report},
  year={2010},
  pages={67-71}
}
The influence of interconnects and the pad stack on measured Metal-Oxide-Semiconductor (MOS) transistor parameter and their reliability degradation cannot always be neglected. The underlying effect is Plasma-Induced-Damage (PID) from the parasitic antennas connected to the MOS gate electrode. Usually, a protection diode is employed to avoid this. However, for some stress and measurement sequences a diode at the gate is not desirable. An alternative method - a layout optimisation is presented… CONTINUE READING

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