MOS C-V characterization of ultrathin gate oxide thickness (1.3-1.8 nm)

@article{Choi1999MOSCC,
  title={MOS C-V characterization of ultrathin gate oxide thickness (1.3-1.8 nm)},
  author={Chang-Hoon Choi and Jung-Suk Goo and Tae-Young Oh and Zhiping Yu and R. V. Dutton and A. H. Bayoumi and Min Cao and P. V. Voorde and Dieter Vook and C. D{\'i}az},
  journal={IEEE Electron Device Letters},
  year={1999},
  volume={20},
  pages={292-294}
}
An equivalent circuit approach to MOS capacitance-voltage (C-V) modeling of ultrathin gate oxides (1.3-1.8 nm) is proposed. Capacitance simulation including polysilicon depletion is based on quantum mechanical (QM) corrections implemented in a two-dimensional (2-D) device simulator; tunneling current is calculated using a one-dimensional (1-D) Green's function solver. The sharp decrease in capacitance observed for gate oxides below 2.0 nm in both accumulation and inversion is modeled using… CONTINUE READING

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