author={Swapnil Haria and Mark D. Hill and Michael M. Swift},
  journal={Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems},
  • Swapnil Haria, Mark D. Hill, M. Swift
  • Published 9 March 2020
  • Mathematics
  • Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems
: Using Fourier analysis, we study local limit theorems in weak-convergence problems. Among many applications, we discuss random matrix theory, some probabilistic models in number theory, the winding number of complex Brownian motion and the classical situation of the central limit theorem, and a conjecture concerning the distribution of values of the Riemann zeta function on the critical line. Using Fourier analysis, we study local limit theorems in weak-convergence problems. Among many… 
3 Citations

A Fast, General System for Buffered Persistent Data Structures

This work presents what it believes to be the first general-purpose approach to building buffered persistent data structures, and a system, Montage, to support that approach, built on top of the Ralloc nonblocking persistent allocator.

COSPlay: Leveraging Task-Level Parallelism for High-Throughput Synchronous Persistence

This work introduces COSPlay, a software-hardware co-design that employs coroutines and rapid userspace context switching to hide persist latency by overlapping persist operations across concurrent tasks.

Single Dose of an mRNA Severe Acute Respiratory Syndrome Coronavirus 2 (SARS-Cov-2) Vaccine Is Associated With Lower Nasopharyngeal Viral Load Among Nursing Home Residents With Asymptomatic Coronavirus Disease 2019 (COVID-19)

In nursing home residents with asymptomatic COVID-19 diagnosed through twice-weekly surveillance testing, single-dose BNT162b2 vaccination (Pfizer-BioNTech) was associated with −2.4 mean log10



The PARSEC benchmark suite: Characterization and architectural implications

This paper presents and characterizes the Princeton Application Repository for Shared-Memory Computers (PARSEC), a benchmark suite for studies of Chip-Multiprocessors (CMPs), and shows that the benchmark suite covers a wide spectrum of working sets, locality, data sharing, synchronization and off-chip traffic.

RRB vector: a practical general purpose immutable sequence

The RRB-Vector is presented, an immutable sequence collection that offers good performance across a large number of sequential and parallel operations and compares favorably to the most important immutable sequence collections in the literature and in use today.

Efficient persist barriers for multicores

This paper proposes an efficient persist barrier, that reduces the number of cache line flushes happening in the critical path, and uses it to enforce two persistency models: buffered epoch persistency with programmer inserted barriers; and buffered strict persistency in bulk mode with hardware inserted barriers.

Better I/O through byte-addressable, persistent memory

A file system and a hardware architecture that are designed around the properties of persistent, byteaddressable memory, which provides strong reliability guarantees and offers better performance than traditional file systems, even when both are run on top of byte-addressable, persistent memory.

Hiding the long latency of persist barriers using speculative execution

This work describes how a new set of persistence instructions work and how they can be used to implement write-ahead logging based transactions and proposes a speculative persistence architecture that reduces the execution time overheads to only 3.6%.

Atlas: leveraging locks for non-volatile memory consistency

This paper identifies failure-atomic sections of code based on existing critical sections and describes a log-based implementation that can be used to recover a consistent state after a failure, and confirms the ability to rapidly flush CPU caches as a core implementation bottleneck and suggest partial solutions.

DudeTM: Building Durable Transactions with Decoupling for Persistent Memory

DUDETM is presented, a crash-consistent durable transaction system that avoids the drawbacks of both undo logging and redo logging and can be implemented with existing hardware TMs with minor hardware modifications, leading to a further 1.7times speedup.

An Analysis of Persistent Memory Use with WHISPER

The Hands-off Persistence System (HOPS) is proposed to track updates to PM in hardware to provide high-level ISA primitives for applications to express durability and ordering constraints separately and enforces them automatically, while achieving 24.3% better performance over current approaches to persistence.

Physical integrity in a large segmented database

A recovery scheme is first proposed for system failure (hardware or software error which causes the contents of main storage to be lost) and a facility for protection against damage to the auxiliary storage itself is proposed.

Proteus: A Flexible and Fast Software Supported Hardware Logging approach for NVM

This paper proposes a new logging approach, Proteus for durable transactions that achieves the favorable characteristics of both prior software and hardware approaches and adds hardware support, primarily within the core, to manage the execution of these instructions.