MLP-aware dynamic instruction window resizing for adaptively exploiting both ILP and MLP

@article{Kora2013MLPawareDI,
  title={MLP-aware dynamic instruction window resizing for adaptively exploiting both ILP and MLP},
  author={Yuya Kora and Kyohei Yamaguchi and Hideki Ando},
  journal={2013 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)},
  year={2013},
  pages={37-48}
}
It is difficult to improve the single-thread performance of a processor in memory-intensive programs because processors have hit the memory wall, i.e., the large speed discrepancy between the processors and the main memory. Exploiting memory-level parallelism (MLP) is an effective way to overcome this problem. One scheme for exploiting MLP is aggressive out-of-order execution. To achieve this, large instruction window resources (i.e., the reorder buffer, the issue queue, and the load/store… CONTINUE READING
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