MIPA4k: A 64×64 cell mixed-mode image processor array

@article{Poikonen2009MIPA4kA6,
  title={MIPA4k: A 64×64 cell mixed-mode image processor array},
  author={Jonne Poikonen and Mika Laiho and Ari Paasio},
  journal={2009 IEEE International Symposium on Circuits and Systems},
  year={2009},
  pages={1927-1930}
}
This paper presents the MIPA4k, a 64×64 cell mixed-mode image processor array chip. The processor cell includes an image sensor, A/D/A conversion, embedded digital and analog memories and hardware-optimized grayscale and binary processing cores. This paper presents the architecture of the processor cell and the different functional hardware. The processor has been manufactured in a 0.13 micron CMOS technology and the chip size is 5.1×4.5 mm2 with a cell area of 72×61 µm2. 
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3 Excerpts

Absolute Value Extraction and Order Statistic Filtering for a Mixed-Mode Array Image Processor

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