MATCHUP: Memory Abstractions for Heap Manipulating Programs

Abstract

Memory-intensive implementations often require access to an external, off-chip memory which can substantially slow down an FPGA accelerator due to memory bandwidth limitations. Buffering frequently reused data on chip is a common approach to address this problem and the optimization of the cache architecture introduces yet another complex design space. This… (More)
DOI: 10.1145/2684746.2689073
View Slides

Topics

4 Figures and Tables

Statistics

0102030201520162017
Citations per Year

Citation Velocity: 9

Averaging 9 citations per year over the last 3 years.

Learn more about how we calculate this metric in our FAQ.

Slides referencing similar topics