MATCHUP: Memory Abstractions for Heap Manipulating Programs


Memory-intensive implementations often require access to an external, off-chip memory which can substantially slow down an FPGA accelerator due to memory bandwidth limitations. Buffering frequently reused data on chip is a common approach to address this problem and the optimization of the cache architecture introduces yet another complex design space. This… (More)
DOI: 10.1145/2684746.2689073
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