M*N Booth encoded multiplier generator using optimized Wallace trees

@article{FadaviArdekani1992MNBE,
  title={M*N Booth encoded multiplier generator using optimized Wallace trees},
  author={Jalil Fadavi-Ardekani},
  journal={Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors},
  year={1992},
  pages={114-117}
}
The architecture and the design method for an M-*-N Booth-encoded parallel-multiplier generator are discussed. An algorithm for reducing the delay inside the branches of the Wallace tree section is presented and explained. The final stage of adding two (N+M-1)-bit numbers is done by an optimal carry-select adder stage. An algorithm for optimal partitioning of the (N+M-1)-bit adder is also presented.<<ETX>> 

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