Low-power variation-aware flip flop

  title={Low-power variation-aware flip flop},
  author={Youngkyu Jang and Changnoh Yoon and Jinsang Kim and Won-Kyung Cho},
  journal={2012 IEEE International Symposium on Circuits and Systems},
Parameter variations in nanometer process technology are one of the major design challenges. They cause to be increased delay on the critical path and to change the logic level of internal nodes. The basic concept to solve these problems at the circuit level, design-for-variability (DFV), is to add error handling circuits at the conventional circuits so that they are robust to nanometer related variations. The state-of-the-art variation-aware flip flops are mainly evolved from aggressive DVFS… CONTINUE READING