Low power noise tolerant domino 1-bit full adder

@article{Meher2014LowPN,
  title={Low power noise tolerant domino 1-bit full adder},
  author={Preetisudha Meher and Kamala Kanta Mahapatra},
  journal={2014 International Conference on Advances in Energy Conversion Technologies (ICAECT)},
  year={2014},
  pages={125-129}
}
A new low power dynamic CMOS one bit full adder cell is presented in this paper. In this design technique is based on semi-domino logic. This new adder cell was compared with some previous proposed widely used dynamic adders as well as other conventional architectures. Objective of this work is to inspect the power, delay, power-delay product and leakage performance of low voltage full adder cells in different CMOS logic styles. Simulation results demonstrate the superiority of the proposed… CONTINUE READING

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