Low-power level converting flip-flop with a conditional clock technique in dual supply systems

@article{Shen2014LowpowerLC,
  title={Low-power level converting flip-flop with a conditional clock technique in dual supply systems},
  author={Ji-Zhong Shen and Liang Geng and Guang-Ping Xiang and Jianwei Liang},
  journal={Microelectronics Journal},
  year={2014},
  volume={45},
  pages={857-863}
}
Abstract Clustered voltage scaling (CVS) is an effective way to reduce power consumption in digital integrated circuits. Level-converting flip-flops are the critical elements in the CVS scheme. In this paper a single edge implicit pulse-triggered level-converting flip-flop with a conditional clock technique (CC-LCFF) is proposed and proved to be suitable for use in low-power non-critical paths with Dual-VDD. CC-LCFF conditionally blocks the clock signal when the input data does not make any… CONTINUE READING

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Key Quantitative Results

  • 9 (a) indicates that the proposed CC-LCFF has 72.37%, 72.40% and 69.41% reductions in power consumption when α is equal to 10% as compared with PHL-LCFF, SP-LCFF and CPN-LCFF.
  • It indicates that CC-LCFF has improvement of 47.73%, 36.74% and 23.36% when data switching activity is 10% and output load is 14 as compared with PHL-LCFF, SP-LCFF and CPN-LCFF.
  • Compared with published pulse triggered level-converting flipflops, post-layout simulation results show that CC-LCFF consumes less power under low data switching activities and is able to gain an improvement of up to 72.40% in power consumption when the activity factor is 10%.

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References

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