Low-power fixed-width array multipliers

@article{Wang2004LowpowerFA,
  title={Low-power fixed-width array multipliers},
  author={Jinn-Shyan Wang and Chien-Nan Kuo and Tsung-Han Yang},
  journal={Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)},
  year={2004},
  pages={307-312}
}
A fixed-width multiplier using the left-to-right algorithm for partial-product reduction is presented. The high-speed feature offered by this design is used to trade for low power. In one design, the proposed multiplier not only owns 8% speed improvement but also gains 14% power and 13% area reduction. When applying the voltage scaling to balance the speed, the power reduction is increased to 29%. 
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