Low power embedded DRAM using 0.6V super retention mode with word line data mirroring

@article{Iwai2009LowPE,
  title={Low power embedded DRAM using 0.6V super retention mode with word line data mirroring},
  author={Takayuki Iwai and Mariko Kaku and Takayuki Miyazaki and Hitoshi Iwai and Hiroyuki Takenaka and Atsushi Suzuki and Shinji Miyano and Mototsugu Hamada},
  journal={2009 IEEE Asian Solid-State Circuits Conference},
  year={2009},
  pages={209-212}
}
An 88% reduction of refresh power of the 65nm embedded DRAM is achieved using Super Retention Mode (SRM) with Word Line Data Mirroring(WLDM). The retention time in Super Retention Mode is measured in the range of 0.55V to 1.2V. The minimum refresh power is obtained at 0.6V. The retention time of Super Retention Mode at 0.6V is extended by 4.1 times from… CONTINUE READING